Semiconductor memory integrated circuits, such as EEPROM, EPROM, FLASH and DRAM, have traditionally been used to store a single digital bit per memory cell, which is termed hereafter as single bit storage. Memories capable of storing more than one bit of digital data per memory cell and their benefits have been described previously. Such multiple bit per cell memories are called multilevel memories because they require more than the conventional two (conducting vs. non-conducting) cell threshold voltage, V.sub.T, levels that are used for single bit storage techniques.
Each level in a multilevel memory cell represents a specific range of electrical charge stored in each memory cell and, in the case of nonvolatile memories, i.e., EEPROM, EPROM, and FLASH memories, represents a specific range of cell V.sub.T values. To store N bits per memory cell requires the cell's V.sub.T range, and the amount of stored charge, to be divided into 2.sup.N levels. Each level corresponds to a unique binary data pattern for all N bits. The cell is erased or programmed to store charge such that the cell's V.sub.T is set within one of these 2.sup.N levels. Sensing circuits determine which level the storage cell's V.sub.T is in and read out the corresponding binary data pattern stored for the N bits. Digital information can thus be stored at a significantly lower cost per bit since N times the number of bits can be stored in the same memory cell array area previously storing just a single bit per cell.
In the following description for nonvolatile memory, a "level" is referred to as a range of V.sub.T values and not as a single voltage value. Furthermore, the term, cell V.sub.T, is not used in the strictest sense defined by solid state device physics, but rather in terms of how the sensing circuits determine the conductivity state of the memory cell. The conductivity is related to the V.sub.T of the cell. Similarly, a DRAM level represents a range of stored charge and not a single charge value.
The operation of sensing individual levels is performed by comparing the conductivity (or stored charge) of the memory cell in terms of sensing voltage or current with respect to multiple reference voltages or currents. The present invention is described in terms of voltage sensing since currents can easily be converted to voltages via load circuits by those practiced in the art of sensing schemes.
There are many problems associated with multilevel memories. Typically 2.sup.N -1 or 2.sup.N reference voltage values, V.sub.RI, where I=1, 2, . . . , 2.sup.N -1, or 2.sup.N, have been proposed to store N bits per memory cell to separate the 2.sup.N levels from each another, with V.sub.R1 &lt;V.sub.R2 &lt; . . . &lt;V.sub.R(2.sup.N.sub.). It should be noted that a V.sub.RI is sometimes referred to as simply V.sub.R for brevity. The relationship between reference voltage values and cell V.sub.T are illustrated in FIGS. 1A-1C, which show the multilevel sensing reference voltages and cell V.sub.T distributions for a whole memory chip for single, two, and four bits stored per cell respectively.
An undesirable condition occurs when a memory cell V.sub.T is close to one of the V.sub.R voltages. The determination of the cell V.sub.T becomes ambiguous. Practical sensing circuits that determine cell V.sub.T are limited by circuit stability and speed, and by voltage and current variations caused by digital switching noise and other variations in power supply voltage, temperature, and silicon processing. Unlike analog signal storage, which does not require discrete multiple levels nor multiple reference voltages, digital memory storage techniques require the level to be unambiguously determined and requires such discrete reference voltages. If the level in a cell is incorrectly sensed, the digital memory malfunctions and up to N bits per cell may be lost.
To avoid the problems of sensing cell V.sub.T values close to, or equal to, one of the V.sub.R voltages, a margin voltage range, V.sub.MPI (see FIG. 2), to separate the cell's V.sub.T in one level from other adjacent levels has been proposed. This separation is performed at the time the cell is erased and programmed. However, both ends of each V.sub.MPI range are not defined. Rather, this proposed technique uses statistical control over the silicon process in conjunction with a lengthy programming algorithm to create adequate V.sub.MPI for storing a single bit, and possibly two bits, per cell. Additionally, no mechanism exists to determine if a cell V.sub.T overshoots the desired range. However, the technique is reliable only when two conditions are met. First, the separation between V.sub.R values must be large enough to provide adequate margin for unambiguous sensing. Secondly, the cell's V.sub.T must remain stable within the desired level and for as long as the data is to remain valid. This period may be as long as the lifetime of the memory chip.
However, a problem all multilevel storage techniques must overcome is the control of the V.sub.T of the memory cell within a very narrow range for each level. This V.sub.T control problem applies to all operational modes of the memory, including programming, erasing and reading the memory cells. The severity of the V.sub.T control problem increases geometrically as the number of bits stored per memory cell increases since 2.sup.N levels per cell are required to store N bits per cell. The range of V.sub.T values within a single level, V.sub.L, and the margin range separating the cell V.sub.T in different levels, V.sub.M (see FIGS. 3A-C), narrows as the number of levels increase within a fixed range of all useful cell V.sub.T values, V.sub.F. In this invention we sometimes refer to a V.sub.LI (where I is one of the 2.sup.N levels) as simply V.sub.L, for brevity's sake.
V.sub.F is usually fixed since it is limited by the voltage range that can be applied to the terminals of the memory cell during the program, erase, and sensing operations. V.sub.F is constrained by circuit speed, complexity and data storage reliability. For many previously proposed nonvolatile memory technologies, V.sub.F is roughly equal to the power supply voltage for read operation, V.sub.CC.
For the extremely simple case where the V.sub.L range for all levels are defined to be the same and there is zero margin between levels, V.sub.L =V.sub.F /2.sup.N. For example, the V.sub.L range for a single bit storage technique operating from a 5 volt V.sub.CC is 5/2=2.5V, while the V.sub.L range for a 4-bit per cell multilevel memory operating from 3V reduces to 3/16=187.5 mV. If a margin voltage range, V.sub.M, is added between each level, V.sub.F =V.sub.L1 +V.sub.M1 +V.sub.L2 +V.sub.M2 + . . . +V.sub.M(2.sup.N.sub.-1) +V.sub.L(2.sup.N.sub.). Continuing with the previous simple case and assuming all V.sub.M ranges are also equal, the level range now reduces to V.sub.L =V.sub.F -(2.sup.N -1).times.V.sub.M !/2.sup.N. With the introduction of a V.sub.M equal to 0.1V, the V.sub.L in the previous 4-bit, 3-volt V.sub.CC example is now reduced to 3-(15.times.0.1)!/16=93.8 mV.
Adding to the V.sub.T control problem is the procedure for erasing memory cells. In practical embodiments of memory arrays, the erasure of cells is accomplished in blocks containing many cells so the V.sub.T distribution of the fully erased cells is wider than the other levels that are programmed more selectively. The wider V.sub.L level used to define the fully erased cells, V.sub.LERASE, reduces the V.sub.L range for the programmed levels even further. FIGS. 3A through 3C graphically illustrate this problem for the same technologies shown in FIGS. 1A-1C.
It should be noted that FIGS. 1A, 1B, 1C, 2, 3A, 3B, and 3C are examples of technologies where programming increases the cell V.sub.T. The previous statements apply analogously for technologies that decrease the cell V.sub.T during programming. In this case these drawings would show the wider erased level at the high end of cell V.sub.T, instead of the low end.
Thus, V.sub.T control is much more important in multilevel than in single bit storage systems since the range of V.sub.T in each level is geometrically reduced as the number of bits per cell increases.
Furthermore, there are various mechanisms which can cause the cell's V.sub.T to drift away from its initially programmed value. Many of these mechanisms are caused by the application of voltage stresses to the cell subsequent to its original programming. These conditions are called "disturbs" and are unavoidable when the cell is grouped within an array of other similar cells to make a useful memory system. Program and erase disturbs are present for the shortest cumulative time but are important causes of V.sub.T drift due to the high voltages used during these operations. For example, disturb data is routinely reported in the technical literature describing new FLASH memory technology.
Other sources of V.sub.T drift are due to the effects of changes in the numbers or positions of trapped charges around the floating gate or between the floating gate and substrate of the memory cell. Trapped charges may be due to defects or the cumulative effects of high electric fields applied over time, such as during repeated program/erase (P/E) cycles. The more erase or programming currents are driven through a gate dielectric, the more trapped charges accumulate. This leads eventually to the retardation of those operations and a malfunction of the part.
Trapped charge may also occur in an unrepeatable fashion with P/E cycling. This has been attributed to the so called "rogue bit" effect. A rogue bit exhibits a shift in programming or erase ability on one cycle and reverts back to normal on another cycle. The rate of V.sub.T drift may not be constant over time and may not be the same from cell to cell due to the statistical variations of the defects present. Each cell in a memory cell array experiences its own unique combination of disturb and charge stress conditions since different rows and columns, within which the cells are interconnected, are accessed in various orders. The drift effects caused by random voltage stresses are added to the drift effects caused by the random defects. These effects are cumulative on the cell's V.sub.T drift.
Nonvolatile cells eventually loose endurance with repeated P/E cycles, that is, they program or erase too slowly for the time allowed for these operations and eventually fail. Some previous programming techniques count the number of times a particular section of memory cell array has been cycled. Such cycling data is then used, in one example, to prevent further P/E cycling of that overused section of memory cell array based on a predetermined conservative maximum number of cycles. This programming technique may thus act to reduce the functionality of the memory before being necessary.
Finally, all the V.sub.T disturb and drift mechanism problems described above worsen due to the increasing electric fields in the cell as the physical sizes of memory cells are reduced. These problems are known impediments to the scaling of cells and barriers to more economical memory chips. Cell V.sub.T drift problems become even more severe as the V.sub.L range is narrowed when storing multiple bits per cell or lower power supply voltages are used, for example.
The present invention solves or substantially mitigates these problems. A memory according to the present invention directly measures the stability, programmability, and erasability of each nonvolatile memory cell over the life of the part.